The 3 nm process is the next step in semiconductor manufacturing after the 5 nm MOSFET technology node. Samsung has already started shipping its 3 nm gate all around (GAA) process, called 3GAA, since mid-2022. TSMC also announced that volume production using its 3 nm semiconductor node, N3, is underway with good yields. Additionally, an enhanced 3 nm chip process called N3E may start production in 2023. Intel plans to join the 3 nm production game in 2023.
Samsung is utilizing GAAFET technology, a type of multi-gate MOSFET technology, for their 3 nm process, while TSMC is still using FinFET technology for their 3 nm process, despite having developed GAAFET transistors. Samsung's variant of GAAFET is called MBCFET. On the other hand, Intel's "Intel 3" process will use an improved version of FinFET technology, with enhancements in performance per watt, use of EUV lithography, and improvements in power and area.
The label "3 nanometer" does not correspond to any specific physical attribute of transistors, such as gate length, metal pitch, or gate pitch. However, the 2021 edition of the International Roadmap for Devices and Systems, published by IEEE Standards Association Industry Connection, predicts that a 3 nm node will have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.
In the world of commercial microchip manufacturing, the term "3 nm" is primarily used as a marketing tool by individual manufacturers to promote a new and improved generation of silicon semiconductor chips. This new generation boasts increased transistor density, higher levels of miniaturization, faster speeds, and reduced power consumption. However, there is no industry-wide consensus on what defines a 3 nm node, and different manufacturers use their own previous process nodes as a basis for comparison. For instance, TSMC claims that its 3 nm FinFET chips will reduce power consumption by 25-30% at the same speed, increase speed by 10-15% at the same power, and increase transistor density by about 33% compared to its previous 5 nm FinFET chips. Meanwhile, Samsung claims that its 3 nm process will reduce power consumption by 45%, improve performance by 23%, and decrease surface area by 16% compared to its previous 5 nm process. However, the use of EUV lithography at 3 nm presents new challenges that require the use of multipatterning.
In 1985, a research team from Nippon Telegraph and Telephone (NTT) created a MOSFET (NMOS) device with a 150 nm channel length and a 2.5 nm gate oxide thickness. Later in 1998, a team from Advanced Micro Devices (AMD) fabricated a MOSFET (NMOS) device with a 50 nm channel length and a 1.3 nm oxide thickness.
Moving forward to 2003, a research team at NEC successfully fabricated MOSFETs with a 3 nm channel length using both PMOS and NMOS processes. This was followed by a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center in 2006, who developed the world's smallest nanoelectronic device - a 3 nm width multi-gate MOSFET based on gate-all-around (GAAFET) technology.
TSMC revealed its intention to build a semiconductor fabrication plant capable of producing 5 nm-3 nm nodes in late 2016, with a co-commitment investment of approximately US$15.7 billion. The construction of the 3 nm semiconductor fabrication plant at the Tainan Science Park in Taiwan was announced by TSMC in 2017, with plans to commence volume production of the 3 nm process node in 2023. In early 2018, IMEC and Cadence announced that they had taped out 3 nm test chips using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography. Samsung presented plans to manufacture 3 nm GAAFET at the 3 nm node in 2021, using its own MBCFET transistor structure that uses nanosheets, in early 2019. Intel announced its plans for 3 nm production in 2025 in December 2019. Samsung announced the production of the world's first 3 nm GAAFET process prototype in January 2020 and stated that it aimed to achieve mass production in 2021. Samsung's semiconductor roadmap also included products at 8, 7, 6, 5, and 4 nm process.
TSMC revealed its N3 3 nm process in August 2020, which is a new process rather than an improvement over its N5 5 nm process. The N3 process is expected to provide a 10-15% increase in performance or a 25-35% decrease in power consumption compared to the N5 process. It also offers a 1.7x increase in logic density, a 20% increase in SRAM cell density, and a 10% increase in analog circuitry density. However, since many designs include more SRAM than logic, die shrinks are expected to be only around 26%. TSMC plans to begin volume production in the second half of 2022.
In July 2021, Intel unveiled a new process technology roadmap. The Intel 3 process, which is the company's second node to use EUV and the last one to use FinFET before switching to Intel's RibbonFET transistor architecture, is now scheduled to enter the product manufacturing phase in H2 2023.
Samsung announced in October 2021 that it would begin producing its customers' first 3 nm-based chip designs in the first half of 2022, after adjusting earlier plans. The company also stated that its second generation of 3 nm chips is expected to be released in 2023.
During the TSMC Technology Symposium in June 2022, the company revealed details about its N3E process technology, which is set to begin volume production in the second half of 2023. This technology boasts a 1.6× higher logic transistor density, a 1.3× higher chip transistor density, and a 10-15% higher performance at iso power or 30-35% lower power at iso performance compared to TSMC N5 v1.0 process technology. Additionally, TSMC introduced new members of the 3 nm process family, including the high-density variant N3S, high-performance variants N3P and N3X, and N3RF for RF applications. The FinFLEX technology allows for the intermixing of libraries with different track heights within a block.
Samsung began producing a low-power, high-performance chip using 3 nm process technology with GAA architecture in June 2022. Qualcomm has reportedly reserved some of Samsung's 3 nm production capacity, according to industry sources.
On July 25, 2022, Samsung announced the first shipment of 3 nm Gate-All-Around chips to a Chinese cryptocurrency mining firm, PanSemi. The new 3 nm MBCFET process technology offers a 16% higher transistor density, 23% higher performance, or 45% lower power draw compared to an unspecified 5 nm process technology. Samsung aims to achieve up to 35% higher transistor density with the second-generation 3 nm process technology, while also reducing power draw by up to 50% or increasing performance by 30%.
TechInsights, a semiconductor industry research firm, reported in July 2023 that MicroBT, a Chinese manufacturer, has integrated Samsung's 3 nm GAA (gate-all-around) process into their crypto miner ASIC (Whatsminer M56S++).
On September 7, 2023, TSMC and MediaTek revealed that MediaTek has created their first 3 nm chip, with volume production set to begin in 2024.
Additionally, on September 12, 2023, Apple announced that the iPhone 15 Pro will be equipped with the A17 Pro, a 3 nm chip.
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